1. Field of the Invention
The present invention relates generally to an apparatus for and a method of receiving broadcasting, and more particularly, to an apparatus for and a method of receiving satellite broadcasting in which an automatic frequency control operation can be precisely performed.
2. Description of the Background Art
In satellite broadcasting which is currently carried out in Japan, a video signal of the NTSC (National Television System Committee) standard is FM-modulated, to be transmitted as an FM video signal of 12 GHz band.
On the receiving side, this FM video signal of 12 GHz band is converted into a first intermediate frequency signal of 1 GHz band, and further down-converted into a second intermediate frequency signal of a frequency band including 134.26 MHz and 402.78 MHz. Thereafter, the second intermediate frequency signal is FM-demodulated so that a video signal is output.
The oscillation frequency of a local oscillator for down-conversion is satisfactorily controlled by an AFC circuit (automatic frequency control circuit). A plurality of circuits constitute an AFC loop, to perform an AFC operation. Ordinary AFC utilizes the fact that the level of a direct current signal in a synchronizing signal portion of the video signal output from an FM demodulator corresponds to the frequency of the second intermediate frequency signal. Thus, in the ordinary AFC, this level of the direct current signal is detected and the result of this detection is fed back, thereby to control the oscillation frequency of the local oscillator (see U.S. Pat. No. 4,417,279).
However, the direct current signal has the disadvantage of being affected by a drift or the like. Therefore, a technique is considered in which the frequency of the second intermediate frequency signal (referred to as second IF signal hereinafter) is counted and data obtained by this counting is fed back, to control the frequency of the local oscillator.
Referring to FIGS. 1 and 2, this example will be briefly described.
In FIG. 1, a BS (broadcasting satellite) antenna 10 comprises an antenna portion 11 and a first converter 12. The antenna portion 11 is, for example, a parabolic antenna or a plane antenna. The first converter 12 comprises an oscillator 13 and a mixer 14. In the first converter 12, a satellite broadcasting signal (FM video signal) of 12 GHz band received by the antenna portion 11 is mixed with an output of the oscillator 13 by the mixer 14. Consequently, an FM video signal (first intermediate frequency signal) (referred to as first IF signal hereinafter) of approximately 1 GHz band is output. Fluctuations in the frequency of the first IF signal is allowed to +1.5 MHz. The fluctuations are corrected by an AFC operation.
A BS tuner 16 comprises a second down-converter 18, a PLL (phase locked loop) circuit 30, a microcomputer 32 for channel selection, an FM demodulating block 34, a counter circuit 46, an output processing block 64, and a synchronizing separator circuit 68.
The second down-converter 18 converts a first IF signal into a second IF signal suitable for multichannel, for example, of 402.78 MHz band. The second down-converter 18 comprises amplifiers 20 and 24 for automatic gain control, a mixer 22, a variable oscillator 26, and a prescaler 28 for dividing the frequency into 1/2.
The PLL circuit 30, together with the variable oscillator 26 and the prescaler 28, constitutes a PLL. The microcomputer 32 switches a frequency dividing ratio of a program divider contained in the PLL circuit 30 to switch a receiving channel, and performs the AFC operation. Meanwhile, a general PLL is well-known, which is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 77533/1985.
The FM demodulating block 34 comprises a second IF filter 36, an amplifier 38, a PLL type FM demodulator 40, an AGC detector 42 for generating an AGC voltage, and a 1/256 frequency divider 44 made of ECL.
The counter circuit 46 directly counts an output signal of the 1/256 frequency divider 44. Resetting and counting operations of the counter circuit 46 is controlled by the microcomputer 32. Count data obtained by the counter circuit 46 is applied to the microcomputer 32.
The output processing block 64 comprises a sound DPSK signal demodulator 48, a PCM decoder 50, a sound output circuit 52, an encoder 54 for digital equipment output, a buffer amplifier 56, a low-pass filter/de-emphasis circuit 58, a disversal circuit 60 for removing a triangular wave, and an output amplifier 62.
The PCM decoder 50 is, for example, TM4218N made by Toshiba Corporation, which comprises a terminal 50a from which an NSYNC signal is output at the time of receiving a sound PCM signal in NTSC broadcasting. The sound output circuit 52 comprises a D/A converter for converting digital signals into analog signals and a low-pass filter.
Furthermore, the BS tuner 16 comprises a group 66 of output terminals. The group 66 of output terminals comprises terminals 66a and 66b for sound output, output terminals 66c and 66d of the DAT optical cable connector specifications, an output terminal 66e for a bit stream, an output terminal 66f for a subscription broadcasting decoder, and a video signal output terminal 66g.
The synchronizing separator circuit 68 extracts a vertical synchronizing signal V.sub.D, to output the same to the microcomputer 32.
Description is made of an operation of the above described BS tuner 16.
In the BS tuner 16, the counter circuit 46 is operated in a predetermined time period, and count data obtained by the counter circuit 46 is input to the microcomputer 32. The microcomputer 32 compares the count data with predetermined reference data, thereby to detect deviation in the frequency of the second IF signal. The microcomputer 32 changes the frequency dividing ratio of the program divider included in the PLL circuit 30 so as to correct the deviation.
The microcomputer 32 determines a predetermined period during which a counting operation is performed by the counter circuit 46 based on the vertical synchronizing signal V.sub.D. This predetermined period is shown in FIG. 2.
In FIG. 2, (a) indicates an output of the PLL type FM demodulator 40, (b) indicates an output of the synchronizing separator circuit 68, (c) indicates a clear signal c1 output from the microcomputer 32 to the counter circuit 46, and (d) indicates a gate signal gate output from the microcomputer 32 for designating the period during which the counting operation is performed by the counter circuit 46.
When the vertical synchronizing signal V.sub.D is input to the microcomputer 32 from the synchronizing separator circuit 68, the microcomputer 32 outputs the clear signal c1. At the same time, the microcomputer 32 outputs the gate signal gate in a vertical synchronization blanking period A (for 1024.mu. seconds), to allow the counting operation of the counter circuit 46. Thereafter, the microcomputer 32 ceases output of the gate signal gate in a period B and then, outputs the gate signal gate again in a period C of 1024.mu. seconds. The microcomputer 32 reads the count data obtained by the counter circuit 46 in the subsequent period D. In order to remove the effect of a triangular wave which is an energy diffusion signal, the microcomputer 32 compares a value obtained by adding four results of counting in a two frame period and dividing the result of the addition by 4 with the value of reference data at the time of receiving NTSC broadcasting, to detect deviation in the frequency of the second IF signal. The microcomputer 32 adjusts the frequency dividing ratio of the PLL circuit 30 based on the deviation. In the above described manner, the AFC operation is performed.
The reason why the counter circuit 46 is operated in a period of is that average value AFC for transmission is employed as a system of controlling the frequency of a main carrier in the case of NTSC broadcasting. In addition, the value of the period B in (d) in FIG. 2 is changed for each field to, for example, 6 m seconds, 4 m seconds, 6 m seconds and 8 m seconds, so that the value of the frequency in each portion on a screen is detected. Consequently, fluctuations caused by variation in brightness are prevented.
The microcomputer 32 controls the PLL circuit 30 for each two frame period, to perform an average value AFC operation. When the PLL circuit 30 is controlled for each field, the previous four results of counting may be averaged and the average value may be compared with the value of the reference data, to perform the AFC operation.
Furthermore, although in the above described example, four results of counting in a four field (two frame) period are averaged, it should be noted that the present invention is not limited to the same. For example, results of counting in a four, six or eight frame period may be averaged.
NHK (Nippon Hoso Kyokai) has developed a MUSE (Multiple Sub-Nyquist Sampling Encoding) system as a system of transmitting a high-definition television signal. This MUSE system uses a MUSE signal obtained by converting a high-definition television signal using a technique for bandwidth compression. In the above described BS tuner, if a satellite broadcasting signal obtained by FM-modulating the MUSE signal is to be received, the number of fields respectively having count values to be averaged, which is different from that in the NTSC system, is determined to the cycle of an energy diffusion signal for the MUSE signal.
Additionally, if and when the MUSE signal is received, a period during which the counter circuit 46 is operated is changed to a clamp level period in the MUSE signal. The MUSE signal is described in an article by Yuichi Ninomiya in Nippon Hoso Kyokai entitled "Transmission System MUSE in High-Definition Television Broadcasting" in Nikkei Electronics published by Nikkei McGraw-Hill Company, No. 433, Nov. 2, 1987, pp. 189-212, which is a well-known technique.
However, the clamp level period in the MUSE signal is 23.mu. seconds, which is very much shorter than a blanking period (1024.mu. seconds) in an NTSC broadcasting signal. A period during which a counter circuit is operated in the clamp level period in the MUSE signal is even shorter, i.e., 15 to 17.mu. seconds. Therefore, it is difficult to perform the AFC operation with high precision by the result of counting in this period.
More specifically, at the time of receiving MUSE broadcasting, detecting precision of the displacement "deviation" of the second IF signal per counting in the counter circuit is 17 MHz. With such detecting precision, the AFC operation can not be performed.
It is considered that the second IF signal is directly counted by the counter circuit 46 without employing the 1/256 frequency divider 44. However, it is difficult to fabricate a high-speed counter circuit capable of counting a second IF signal of 402.78 MHz even using ECL (emitter coupled logic). Even using the ECL, only the frequency divider 44 for simply dividing the frequency as shown in FIG. 1 can be achieved.
Additionally, it is also difficult to count a signal obtained by frequency-dividing the second IF signal into 1/2 to 1/4 by the frequency divider using the ECL. In addition, if the second IF signal is further frequency-divided, detecting precision per counting is too low, so that a practical problem occurs. The reason is that the amount of fluctuations in the frequency of the second IF signal is simultaneously frequency-divided if the second IF signal is frequency-divided by the frequency divider. Even if the signal frequency-divided into 1/2 or 1/4 can be counted, detecting precision per counting in this case is approximately 130 KHz or approximately 260 KHz.
Therefore, it is considered that the ordinary keyed AFC operation is performed at the time of receiving MUSE broadcasting. FIG. 3 illustrates a BS tuner 16 in which the average AFC operation is performed at the time of receiving NTSC broadcasting and the ordinary keyed AFC operation is performed at the time of receiving MUSE broadcasting.
The BS tuner 16 shown in FIG. 3 further comprises a buffer 72 for a MUSE signal, a sample-and-hold circuit 76 and an A/D converter 78. A MUSE decoder 70 is connected to an output terminal 72a receiving an output of the buffer 72. The MUSE decoder 70 outputs a high definition television signal as well as outputs a keyed AFC pulse signal representing a clamp level period only at the time of inputting a MUSE signal.
The keyed AFC pulse signal P is applied to a keyed AFC pulse signal input terminal (high definition television broadcasting terminal) 74. The sample-and-hold circuit 76 samples the keyed AFC pulse signal P applied to the input terminal 74. The A/D converter 78 converts a value sampled by the sample-and-hold circuit 76 into a digital value.
At the time of receiving MUSE broadcasting, a microcomputer 32 compares a digital value obtained by the A/D converter 78 with the value of reference data used at the time of receiving a MUSE signal, to detect the difference therebetween. The microcomputer 32 controls a PLL circuit 30 based on the difference. In the above described manner, an AFC operation is performed.
However, in the BS tuner 16 shown in FIG. 3, an analog signal is sampled and held at the time of receiving MUSE broadcasting. Therefore, the level of the analog signal sampled and held is affected by the temperature or the like. Consequently, it is impossible to achieve high precision and high response of the BS tuner.